Introducing our cutting-edge end-to-end RISC-V verification infrastructure crafted for co-simulation purposes, Argus-V. Drawing inspiration from Greek mythology, Argus was an "all-seeing" guardian giant, often depicted with a hundred eyes. Argus-V ensures the detection of hundreds of bugs in your RISC-V RTL design.
Texer.AI introduces Argus-V. Drawing inspiration from Greek mythology, Argus was an "all-seeing" guardian giant, often depicted with a hundred eyes. Argus-V ensures the detection of hundreds of bugs in your RTL design.
Argus-V stands as a state-of-the-art microprocessor verification tool, seamlessly integrating into your existing verification infrastructure. It employs a co-simulation approach, where RTL simulator and the emulator execute the same binary simultaneously and communicate through messages.
Argus-V gets instantiated into an RTL design. Then, RTL simulator triggers Argus at instruction commit to commit an instruction at its end and compare relevant states. If there's a mismatch, execution stops immediately, and the problem gets reported. This method eases debugging since engineers can begin their investigation near the point of deviation.
To handle asynchronous interrupts, the system must manage messages that can modify the emulator's execution trajectory. If the RTL detects an interrupt, it should notify the emulator to adjust its execution accordingly.
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